FPGAs are integrated circuits that include logic, processing, memory, and routing resources that may be programmed in the field after manufacture. FPGAs may be used to implement large systems that include millions of gates and megabits of embedded memory. As FPGAs have improved in performance, it has become more common to time-division-multiplex slower or more expensive blocks on the FPGA, such as digital signal processing (DSP) blocks. This has created the need for pipelining on logic paths where successive registers are placed in series without implementing logic components between the registers.
Most FPGAs include logic blocks that have combinational cells and registers that are programmable to implement logic functions. Each logic block may include one or more combinational cells and registers, where the number of combinational cells is typically equal to the number of registers. When pipelining requires data from a first logic path to be synchronized with data from a second logic path or requires data to be registered into numerous stages, additional logic blocks are commonly used to provide the needed registers.
This approach, however, resulted in the use of only the register portion of a logic block and wasting the combinational cell portion of the logic block which was often the larger and more expensive of the components. More unused space would be needed to implement these systems which is inefficient and costly.
Thus, what is needed is an efficient and effective method and apparatus for supporting system designs requiring additional registers on an FPGA.